The present invention relates to a semiconductor memory, and more specifically to a synchronous semiconductor memory having an improved reading margin and an improved timing control in a test mode.
Referring to FIGS. 1A, 1B and 1C, there are shown block diagrams illustrating a control circuit of a data amplifier section of a prior art synchronous semiconductor memory. FIGS. 2A and 2B are timing charts illustrating an operation of the synchronous semiconductor memory shown in FIGS. 1A, 1B and 1C, in different operation conditions.
As shown in FIG. 1A, the prior art synchronous semiconductor memory includes a memory controller 101, a data amplifier controller 602, a memory cell array 103 and a number of data amplifiers 141 to 14n, which are coupled as shown. The memory controller 101 receives a test-CAS (column address strobe) signal "testCAS", a pre-CAS signal "preCAS" and a clock signal CLK, and generates a CAS signal CAS. Here, the pre-CAS signal preCAS is a preceding signal for generating the CAS signal CAS, and is used as the CAS signal CAS in a high frequency operation (actual use condition; on the order of a few ns to a few 10 ns). On the other hand, the test-CAS signal testCAS is used as the CAS signal. CAS in a low frequency operation (test mode condition; on the order of a few 10 ns to a few 100 ns).
The CAS signal CAS is supplied to a NAND gate 104 located before the memory cell array 103, and also to the data amplifier controller 602. This data amplifier controller 602 generates a data amplifier enable signal DAE to the data amplifiers 141 to 14n. On the other hand, the NAND gate 104 receiving the CAS signal CAS also receives an address signal ADR, so that a logical NAND between the CAS signal CAS and the address signal ADR is outputted to an inverter 104a, which outputs a column selector signal YSW to the memory cell array 103. Each of the data amplifiers 141 to 14n is enabled by the data amplifier enable signal DAE to amplify data RT/N from the memory cell array 103 and to output an output signal Dout.
As shown in FIG. 1B, the data amplifier controller 602 comprises a delay 108 and a pair of inverters 609 and 610, which are connected in cascade in the named order as shown. The CAS signal CAS is supplied to the delay 108, and outputted through the two cascaded inverters as the data amplifier enable signal DAE.
Furthermore, as shown in FIG. 1C, the memory controller 101 includes a flipflop 105, a selector 106 and a clock frequency discriminator 107, connected as shown. The pre-CAS signal preCAS and the clock CLK are supplied to the flipflop 105, and an output of the flipflop 105 is supplied to the selector 106. This selector also receives the test-CAS signal testCAS. The clock CLK is also supplied to the clock frequency discriminator 107, and the selector 106 is controlled by the clock frequency discriminator 107 on the basis of the frequency of the clock signal CLK, so that the selector 106 outputs one of the test-CAS signal and the output of the flipflop 105 as the CAS signal CAS.
As mentioned above, the pre-CAS signal preCAS is the preceding signal for generating the CAS signal CAS, and is used in the high frequency operation (actual use condition), and the test-CAS signal testCAS is used as the CAS signal CAS in the low frequency operation (test mode condition). The column selection signal YSW is selected on the basis of the address signal ADR, and activated in time with the CAS signal CAS.
In the memory controller 101, the clock frequency discriminator 107 outputs a high level signal when the clock signal CLK is a high frequency, and a low level signal when the clock signal CLK is a low frequency. When the output of the clock frequency discriminator 107 is at the high level, the selector 106 selects the output of the flipflop 105, and when the output of the clock frequency discriminator 107 is at the low level, the selector 106 selects the test-CAS signal testCAS. Thus, as mentioned above, since the pre-CAS signal preCAS is in the preceding signal for generating the CAS signal CAS, the pre-CAS signal preCAS is used in the high frequency operation (actual use condition). On the other hand, in the low frequency operation (test mode condition), the test-CAS signal testCAS is used as the CAS signal CAS.
Incidentally, the reason for why a low frequency operation is required in the test mode is that, to test a peripheral circuit, a logic tester having a test rate on the order of a few 100 ns is used.
The data amplifier controller 602 outputs the CAS signal CAS through the delay 108 and the inverters 609 and 610 as the data amplifier enable signal DAE.
As shown in FIG. 2A, a time from a rising of the CAS signal CAS to the outputting of the output signal Dout is standardized as a time tdac, which is set to a predetermined value for each product. Here, it is important that after an amplifiable potential difference has been generated in a data signal RT/N (between a pair of complementary signals) outputted from the memory cell array 103, the data amplifiers 141 to 14n are enabled by the data amplifier enable signal DAE, and that the actual time from the rising of the CAS signal CAS to the outputting of the output signal Dout meets with the standardized time tdac.
Here, since a fast condition in which an internal clock operates at a high speed is determined by circuit elements and a use condition of the semiconductor device, and since a slow condition in which an internal clock operates at a slow speed is also determined by the circuit elements and a use condition of the semiconductor device, the time tRT/NC from the rising of the CAS signal CAS to the outputting of the data signal RT/N having the amplifiable potential difference is determined by the fast condition and the slow condition, and therefore, the timing of a rising of the data amplifier enable signal DAE is determined to meet with the time tRT/NC in the fast condition and the slow condition. In a clock synchronization, the difference between the fast condition and the slow condition in the time tDC from the rising of the CAS signal CAS to the rising of the data amplifier enable signal DAE, is larger than the difference between the fast condition and the slow condition in the time rRT/NC from the rising of the CAS signal CAS to the outputting of the data signal RT/N having the amplifiable potential difference. Therefore, if it is so set that in the fast condition, after the data signal RT/N has reached the amplifiable potential difference, the data amplifiers 141 to 14n are enabled by the rising of the rising of the data amplifier enable signal DAE, the access time from the rising of the CAS signal CAS to the outputting of the output signal Dout in the slow condition is required to come within the standardized time tdac.
In the synchronous semiconductor memory as mentioned above, the scale of the memory cell array is increasing with increase of a required memory capacity, with the result that a read path extending in the memory cell array is becoming long. If the read path becomes long, the time from the inputting of the CAS signal until the data is outputted to the data amplifier becomes long. If the data amplifier enable signal DAE is generated to meet with this timing by delaying the CAS signal by use of a delay element, a long delay becomes required from the inputting of the CAS signal to the activation of the data amplifier enable signal DAE, and correspondingly, variation in the timing for enabling the data amplifiers becomes large because of a process variation and changes in temperature and in voltage. As a result, possibility that the access time becomes out of the standardized time tdac will increase.
If the rising of the data amplifier enable signal DAE is adjusted to meet with the fast condition as shown in FIG. 2A, the time tDC from the rising of the CAS signal to the rising of the data amplifier enable signal DAE in the slow condition becomes too long, so that the access time comes out of the standardized time tdac, as shown in FIG. 2B. On the other hand, if the rising of the data amplifier enable signal DAE was so adjusted that the access time comes within the standardized time tdac in the slow condition, it results in that in the fast condition the data amplifier enable signal DAE is risen before the data signal RT/N has reached the amplifiable potential difference, with the result that the activated data amplifiers 141 to 14n erroneously sense the data outputted from the memory cell array.